Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domains. The impact of metastability is becoming increasingly important as process geometries shrink and supply voltages are being lowered, while transistor $V_t$'s are not being scaled as aggressively. FPGAs technologies are significantly affected in this regard due to the fact that leading edge FPGAs are often the first devices to adopt the most recent process nodes. In this paper, we present a comprehensive suite of techniques for modeling, characterizing and optimizing for metastability effects in FPGAs. We first discuss a theoretical model for describing metastability, and verify this using both circuit level simulations and board measurements. Next we show how designers have traditionally dealt with metastability problems and contrast that with the automatic CAD algorithms described in this paper that both analyze and optimize metastability-related issues. Through our detailed experimental results, we show that we can improve the metastability characteristics of a suite of industrial benchmarks by an average of 268,000 times through our optimization techniques.