Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed on all feedback paths to ensure proper synchronization between the TMR replicates when configuration SEUs are repaired. Synchronization voters, however, consume additional resources and impact system timing. This paper will introduce and contrast seven algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks will be described. This paper will demonstrate that algorithms which insert voters directly after flip-flops perform better than the other algorithms. Specifically, the increase in critical path length over an untriplicated design is only 15.8% for these algorithms compared to 29.6% for the other algorithms.