As the IC technology scales down to nanometer range, the increased manufacturing variations make the traditional Static Timing Analysis (STA) inaccurate. Statistical Static Timing Analysis (SSTA) is proposed to overcome the inaccuracy caused by the variation. Among different SSTA methods, Monte Carlo based SSTA provides an accurate analysis of circuit delay (with large enough samples), and serves as the golden standard for all other methods to compare with. But due to high computation time, it is seldom used in practice. As an attempt to address this problem, we propose an FPGA-based acceleration using the state-of-the-art BEEcube platform to accelerate the Monte Carlo based SSTA. In the SSTA formulation, the output delay of each gate is computed as the max of the sum of the input pin’s arrival time and pin-to-output delay. This allow us to model the entire circuit as a data flow graph, which consists of “max” and “sum” operations. FPGAs, with the ability to implement custom, pipelined data paths appear to be well suited for Monte Carlo based SSTA. The challenge is to fit an efficient implementation on the limited FPGA area. For this, we leverage the techniques of pattern matching and pattern recognition to identify the patterns in the mapped circuit netlist, and then use this information to share hardware resources among the same pattern instances. We formulate the problem of allocating hardware resources for each pattern within the limited FPGA area bound as an optimization problem. By solving this optimization problem, we can obtain the maximum speedup on the limited FPGA area. Our implementation of Monte Carlo based SSTA on BEEcube platform shows significant performance speedup.