A 3D-Audio Reconfigurable Processor

Dimitris Theodoropoulos,  Georgi Kuzmanov,  Georgi Gaydadjiev
Delft Techincal University of Technology


Abstract

Various multimedia communication systems have been proposed by researchers from the acoustic data processing domain that are based on 3D-Audio algorithms. However, all systems reported in the literature follow a PC-based approach that is characterized by processing bottlenecks and increased power consumption. In order to alleviate these problems, we propose a reconfigurable 3D-Audio processor that can record and render sound sources concurrently. Audio recording and rendering are performed by two hardware accelerators tuned for the beamforming and the Wave Field Synthesis algorithms. The theoretical scalability of the proposed processor is explored with respect to systems consisting of different microphone and loudspeaker arrays configurations. A working FPGA prototype is compared against a software implementation on a Core2 Duo. Experimental results suggest that the proposed reconfigurable hardware solution can process data up to 3.6 times faster than the software approach when processing four audio sources, while power consumption is only 7 Watts according to the Xilinx XPower estimation.