FPGA 2010: Program

Sunday Feburary 21, 2010
2:00 PM    Pre-conference Workshop: "Open-Source for FPGA" "Open-Source for FPGA"
Chair: Shep Siegel, Atomic Rules
Co-Chair: Mike Wirthlin, BYU
6:00 PM    Registration
7:00 PM    Reception
Monday Feburary 22, 2010
8:00 PM    Continental Breakfast, Registration
8:40 PM    Opening Remarks
Peter Cheung, Imperial College London
John Wawrzynek, University of California, Berkeley
9:00 AM    Session 1: SoC Implementation
Chair: Jason Cong, University of California, Los Angeles
   Intel Nehalem Processor Core Made FPGA Synthesizable
Graham Schelle,  Jamison Collins,  Ethan Schuchman,  Perry Wang,  Xiang Zou,  Gautham Chinya,  Ralf Plate,  Thorsten Mattner,  Franz Olbrich,  Per Hammarlund,  Ronak Singhal,  Sebastian Steibl,  Hong Wang
Intel
   FPGA Prototyping of an AMBA-base Windows-Compatible SoC
Kan Huang,  Junlin Lu,  Jiufeng Pang,  Yansong Zheng,  Hao Li,  Dong Tong,  Xu Cheng
Microprocessor Research and Development Center of Peking University
   Predicting the Performance of Application-Specific NoCs Implemented on FPGAs
Jason Lee and Lesley Shannon
Simon Fraser University
   (short paper)    Combining Multi-core and Reconfigurable Instruction Set Extensions
Zhimin Chen1,  Richard Pittman2,  Alessandro Forin2
1Virginia Tech, 2Microsoft Research
   (short paper)    Energy Efficient Sensor Node Implementations
Jan Frigo1,  Eric Raby1,  Ed Rosten2,  Vinod Kulathumani3,  Christophe Wolinski4,  Charles Wagner4,  Francois Charot4,  Sean Brennan1
1LANL, 2Dept. of Engineering, University of Cambridge, 3Dept. of Computer Science and Electrical Engineering, West Virginia University, 4University of Rennes, IRISA
10:10 AM    Poster Session 1: Applications
Chair: Russ Tessier, University of Massachusetts at Amherst
11:10 AM    Session 2: High-level Synthesis
Chair: Wayne Luk, Imperial College London
   Efficient Multi-Ported Memories for FPGAs
C. Eric LaForest and J. Gregory Steffan
University of Toronto
   Automatic Generation of High-Performance Multipliers for FPGAs with Asymmetric Multiplier Blocks
Shreesha Srinath and Katherine Compton
University of Wisconsin-Madison
   Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration
Jiyu Zhang1,  Zhiru Zhang2,  Sheng Zhou2,  Mingxing Tan1,  Xianhua Liu1,  Xu Cheng1,  Jason Cong3
1Peking University, 2AutoESL Design Technologies, Inc., 3University of California, Los Angeles
   (short paper)    Designing Hardware with Dynamic Memory Abstraction
Jiri Simsa
Carnegie Mellon University
12:15 PM   
Lunch
2:00 PM    Session 3: Accelerations Engines
Chair: Satnam Singh, Microsoft Cambridge Research
   High-Throughput Bayesian Computing Machine with Reconfigurable Hardware
Mingjie Lin,  Ilia Lebedev,  John Wawrzynek
UC Berkeley
   High Throughput and Large Capacity Pipelined Dynamic Search Tree on FPGA
Yi-Hua Edward Yang and Viktor K. Prasanna
USC/EE
   FPMR : MapReduce Framework on FPGA - a Case Study of RankBoost Acceleration
Yi Shan1,  Bo Wang1,  Jing Yan1,  Yu Wang1,  Ningyi Xu2,  Huazhong Yang1
1Tsinghua University, 2Microsoft Research Asia
   (short paper)    Acceleration of an Analytical Approach to Collateralized Debt Obligation Pricing
Dharmendra Gupta and Paul Chow
Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada
   (short paper)    A 3D-Audio Reconfigurable Processor
Dimitris Theodoropoulos,  Georgi Kuzmanov,  Georgi Gaydadjiev
Delft Techincal University of Technology
   (short paper)    Accelerating Monte-Carlo based SSTA using FPGA
Jason Cong,  Karthik Gururaj,  Wei Jiang,  Bin Liu,  Kirill Minkovich,  Bo Yuan,  Yi Zou
Computer Science Department, University of California, Los Angeles
3:15 PM    Poster Session 2: High-level Abstractions and CAD Tools
Chair: Brad Hutchings, Brigham Young University
4:15 PM    Session 4: Reconfigurable Computing Systems
Chair: Deming Chen, University of Illinois at Urbana-Champaign
   Axel: A Heterogeneous Cluster with FPGAs and GPUs
Kuen Hung Tsoi and Wayne Luk
Imperial College London
   Server-Side Coprocessor Updating for Mobile Devices with FPGAs
Chen Huang and Frank Vahid
University of California, Riverside
   Accurately Evaluating Application Performance in Simulated Hybrid Multi-Tasking Systems
Kyle Rupnow,  Jacob Adriaens,  Wenyin Fu,  Katherine Compton
University of Wisconsin - Madison
5:30 PM    Steering Committee Meeting - Big Sur Room
7:00 PM    Dinner and Evening Panel: " "Programming High Performance Signal Processing Systems in High Level Languages"
Chair: Kees Vissers, Xilinx
Tuesday Feburary 23, 2010
8:30 AM    Session 5: CAD Tools
Chair: Lei He, University of California, Los Angeles
   Towards Scalable Placement for FPGAs
Hannah Bian,  Andrew Ling,  Jianwen Zhu,  Alexander Choong
University of Toronto
   FPGA Power Reduction by Guarded Evaluation
Jason Anderson and Chirag Ravishankar
University of Toronto
   A Comprehensive Approach to Modeling, Characterizing and Optimizing for Metastability in FPGAs
Doris Chen,  Deshanand Singh,  Jeffrey Chromczak,  David Lewis,  Ryan Fung,  David Neto,  Vaughn Betz
Altera Corporation
   (short paper)    Variation-Aware Placement for FPGAs with Multi-cycle Statistical Timing Analysis
Gregory Lucas1,  Chen Dong1,  Deming Chen2
1Graduate Student, 2Professor
   (short paper)    Global Delay Optimization using Structural Choices
Alan Mishchenko1,  Robert Brayton1,  Stephen Jang2
1UC Berkeley, 2n/a
   (short paper)    Building A Faster Boolean Matcher Using Bloom Filter
Chun Zhang1,  Yu Hu2,  Lingli Wang1,  Lei He3,  Jiarong Tong1
1State Key Laboratory of ASIC & System, Fudan University, Shanghai, China, 2University of Alberta, Canada, 3University of California, Los Angeles
9:45 AM    Poster Session 3: Architecture and Design Studies
Chair: Carl Ebeling, University of Washington
10:45 AM    Session 6: High-performance Applications
Chair: John Lockwood, Stanford University
   Haptic Rendering of Deformable Objects using a Multiple FPGA Parallel Computing Architecture
Behzad Mahdavikhah,  Ramin Mafi,  Shahin Sirouspour,  Nicola Nicolici
Department of Electrical & Computer Engineering, McMaster University, Hamilton, Ontario, Canada
   A 1 Cycle-Per-Byte XML Parsing Accelerator
Zefu Dai,  Nick Ni,  Jianwen Zhu
Electrical and Computer Engineering, University of Toronto
   A Modular NFA Architecture for Regular Expression Matching
Hao Wang,  Shi Pu,  Gabe Knezek,  Jyh-Charn Liu
TAMU
   Scalable Network Virtualization Using FPGAs
Deepak Unnikrishnan1,  Ramakrishna Vadlamani1,  Yong Liao1,  Abhishek Dwaraki1,  Jeremie Crenne2,  Lixin Gao1,  Russell Tessier1
1ECE, University of Massachusetts, Amherst, 2European University of Brittany
12:05 PM   
Lunch
1:35 PM    Session 7: Reliability
Chair: Lesley Shannon, Simon Fraser University
   Degradation in FPGAs: Measurement and Modelling
Edward Stott1,  Justin Wong1,  Pete Sedcole2,  Peter Cheung1
1Imperial College London, 2
   On-Line Sensing for Healthier FPGA Systems
Kenneth Zick and John Hayes
University of Michigan
   Voter Insertion Algorithms for FPGA Designs Using Triple Modular Redundancy
Jonathan Johnson and Michael Wirthlin
Brigham Young University
   (short paper)    Maximizing Area-Constrained Partial Fault Tolerance in Reconfigurable Logic
David Foster1 and Darrin Hanna2
1Kettering University, 2Oakland University
2:40 PM   
Break
3:10 PM    Session 8: Architecture
Chair: Jonathan Rose, University of Toronto
   The Impact of Interconnect Architecture on Via-Programmed Structured ASICs (VPSAs)
Usman Ahmed,  Guy Lemieux,  Steve Wilton
University of British Columbia
   Efficient FPGAs using Nanoelectromechanical Relays
Chen Chen1,  Soogine Chong1,  Roozbeh Parsa1,  Nishant Patil1,  Kerem Akarvardar1,  J Provine1,  David Lewis2,  Jeff Watt2,  Roger T. Howe1,  H.-S. Philip Wong1,  Subhasish Mitra1
1Stanford University, 2Altera Corporation
3:50 PM    Closing Remarks