Sunday Feburary 21, 2010
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2:00 PM
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Pre-conference Workshop: "Open-Source for FPGA"
"Open-Source for FPGA"
Chair: Shep Siegel, Atomic Rules
Co-Chair: Mike Wirthlin, BYU
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Monday Feburary 22, 2010
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8:00 PM
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Continental Breakfast, Registration
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8:40 PM
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Opening Remarks
Peter Cheung, Imperial College London
John Wawrzynek, University of California, Berkeley
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9:00 AM
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Session 1: SoC Implementation
Chair: Jason Cong, University of California, Los Angeles
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Intel Nehalem Processor Core Made FPGA Synthesizable
Graham Schelle, Jamison Collins, Ethan Schuchman, Perry Wang, Xiang Zou, Gautham Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Sebastian Steibl, Hong Wang
Intel
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(short paper)
Energy Efficient Sensor Node Implementations
Jan Frigo1, Eric Raby1, Ed Rosten2, Vinod Kulathumani3, Christophe Wolinski4, Charles Wagner4, Francois Charot4, Sean Brennan1
1LANL, 2Dept. of Engineering, University of Cambridge, 3Dept. of Computer Science and Electrical Engineering, West Virginia University, 4University of Rennes, IRISA
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10:10 AM
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Poster Session 1: Applications
Chair: Russ Tessier, University of Massachusetts at Amherst
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11:10 AM
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Session 2: High-level Synthesis
Chair: Wayne Luk, Imperial College London
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Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration
Jiyu Zhang1, Zhiru Zhang2, Sheng Zhou2, Mingxing Tan1, Xianhua Liu1, Xu Cheng1, Jason Cong3
1Peking University, 2AutoESL Design Technologies, Inc., 3University of California, Los Angeles
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2:00 PM
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Session 3: Accelerations Engines
Chair: Satnam Singh, Microsoft Cambridge Research
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3:15 PM
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Poster Session 2: High-level Abstractions and CAD Tools
Chair: Brad Hutchings, Brigham Young University
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4:15 PM
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Session 4: Reconfigurable Computing Systems
Chair: Deming Chen, University of Illinois at Urbana-Champaign
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5:30 PM
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Steering Committee Meeting
- Big Sur Room
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Tuesday Feburary 23, 2010
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8:30 AM
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Session 5: CAD Tools
Chair: Lei He, University of California, Los Angeles
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(short paper)
Building A Faster Boolean Matcher Using Bloom Filter
Chun Zhang1, Yu Hu2, Lingli Wang1, Lei He3, Jiarong Tong1
1State Key Laboratory of ASIC & System, Fudan University, Shanghai, China, 2University of Alberta, Canada, 3University of California, Los Angeles
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9:45 AM
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Poster Session 3: Architecture and Design Studies
Chair: Carl Ebeling, University of Washington
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10:45 AM
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Session 6: High-performance Applications
Chair: John Lockwood, Stanford University
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Scalable Network Virtualization Using FPGAs
Deepak Unnikrishnan1, Ramakrishna Vadlamani1, Yong Liao1, Abhishek Dwaraki1, Jeremie Crenne2, Lixin Gao1, Russell Tessier1
1ECE, University of Massachusetts, Amherst, 2European University of Brittany
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1:35 PM
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Session 7: Reliability
Chair: Lesley Shannon, Simon Fraser University
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3:10 PM
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Session 8: Architecture
Chair: Jonathan Rose, University of Toronto
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Efficient FPGAs using Nanoelectromechanical Relays
Chen Chen1, Soogine Chong1, Roozbeh Parsa1, Nishant Patil1, Kerem Akarvardar1, J Provine1, David Lewis2, Jeff Watt2, Roger T. Howe1, H.-S. Philip Wong1, Subhasish Mitra1
1Stanford University, 2Altera Corporation
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