Introduction to the use of hardware description languages and automated synthesis in design. Advanced design principles. Verilog and VHDL description languages. Synthesis from hardware description languages. Timing-oriented synthesis. Relation of IC layout to timing-oriented design. Design for reuse.
INSTRUCTOR and TEACHING ASSISTANT
Kyle Rupnow
B630 Engineering Hall, 263-1572, kjrupnow@wisc.edu
Office Hours: Tuesday 3-4pm, Wednesday 4-6pm, Thursday 3-4pm in B555 Engineering Hall
CLASS MEETINGS
Discussion Section
Tuesdays, 6:00pm to 7:00pm, 2317 Engr Hall.
Note: Course website will notify on weeks when there will be no discussion section.
COURSE PURPOSE
CREDITS: 3. DESIGN CREDITS: 2.
PREREQUISITES: ECE/CS 352 and Junior Standing.
RESOURCES
Text
M. D. Cilleti, Advanced Digital Design with the Verilog HDL, Prentice
Hall, 2003. (Book web site)
Online Text
P.J. Ashenden, The VHDL Cookbook, 1990. (Available on the course website)
Standards
IEEE Std.1364-2001, IEEE Standard Verilog Hardware Description Language, IEEE, Inc., 2001, and IEEE Std 1364.1-2002, IEEE Standard for Verilog Register Transfer Level Synthesis, IEEE, Inc., 2002.
Available from: http://ieeexplore.ieee.org/ on CAE computers. Click on “Standards”, then search for 1364.
Web Materials
Lecture Notes, Tool Manuals and Tutorials, Links to External Web Sites, Papers, etc.
Course Tools
Modelsim HDL Simulation Tools (Mentor Graphics), Design Vision Synthesis Tools (Synopsys), and the LSI Logic Gflx 0.11 Micron CMOS Standard Cell Library.
Students must sign up for mandatory tool tutorials.
RESPONSIBILITIES
Homework
There will be approximately six homework assignments. Homework is to be turned in by the beginning of class on the due date. Homework turned in at the beginning of the next class after the homework is due will receive a 10% reduction and must be marked on the front page by the student as LATE to receive any credit. After the next class, late homework will not be accepted.
Project
The course project will be performed by teams and will involve the design of a complex digital logic system. The project will be common to all groups and will involve register transfer hardware and significant finite state machine control. Speed and area will be emphasized as well as well-verified functionality. The project may be performed in stages with intermediate results submitted to maintain a schedule. More details will be available in class and on the course website.
Grading
Homework 25%, Midterm 20%, Final 25%, Project 30%. Grade distributions may be varied by up to 5%.
OUTLINE
| Tentative Outline | ||
| Week | Topics | Readings |
| 1 Jan 20 & 22 |
Course Introduction, Overview of Contemporary Digital Design: Electronic Design Automation (EDA), Application Specific Integrated Circuit (ASIC) Technologies, Technology Libraries, ASIC Design and Design Flows, Review of Combinational and Sequential Logic, an Overview of Hardware Description Languages (HDLs), Introduction to Verilog and its Data Types | Text: Read pp. 1-11, Review pp. 13-101 Std: 1, 2, 3-3.3, 3.5-3.6, 3.8-3.11 |
| 2 Jan 27 & 29 |
Verilog 1: Models, Structural Models, Modules, Primitives, Design Hierarchy, Vectors, Logic System, Test Methods, Test Benches and Simulation, Propagation Delay
ModelSim Tutorials, times TBA on course website |
Text: pp. 103-131, 883-887, 895-903, 915, 929-932 Std: 7-7.4, 7.14-7.14.1, 12 Homework #1 |
| 3 Feb 3 & 5 |
Verilog 2: Behavioral Descriptions, Operators, Assignments, Combinational Logic Models, Continuous and Procedural Assignments, Flip-Flop and Latch Models, Styles for Behavioral Modeling | Text: pp. 143-175, 905-913, 932-934 Std: 4, 6 |
| 4 Feb 10 & 12 |
Verilog 3: Behavioral Modeling, Scheduling Semantics, Modeling Specialized Structures | Text: pp. 176-209, 934-937 Std: 5, 9 Homework #2 |
| 5 Feb 17 & 19 |
Verilog 4: Task and Functions, FSM Modeling, Simulation I/O, Compiler Directives, Design Configuration, and 2001 Standard Differences | Text: pp. 945-965 Std: 10, 13, 17-17.4, 17.7, 19.3-19.5, 19.8 |
| 6 Feb 24 & 26 |
MIDTERM on weeks 1-5 VHDL 1: VHDL Introduction, VHDL Datatypes, Operators, and Constructs |
VHDL: ch. 1, 2 Homework #3 |
| 7 Mar 2 & 4 |
VHDL 2: Structural and Behavioral VHDL, VHDL Model Organization | VHDL: ch. 3, 4, 5, 6 |
| 8 Mar 9 & 11 |
Synthesis 1: Introduction to Synthesis, Synthesis of Combinational Logic | Text: pp. 233-258 Std-1: 1 - 5.1 Homework #4 |
| 9 Mar 23 & 25 |
Synthesis 2: Synthesis of Sequential Logic, Three State Devices, Bus Interfaces, Latches and Flip-Flops, Finite State Machines
Design Vision Tutorials, times TBA on course website |
Text: pp. 258-275 Std-1: 5.2-5.7 |
| 10 Mar 30 & |
Synthesis 3: Setting Constraints and Design Optimization | Synopsys On-line Documentation Homework #5 |
| 11 Apr 6 & 8 |
Synthesis 4: State Machines, Registered Logic, Counters, Registers, Resets, Gated Clocks | Text : pp. 275-314 Std-1: 6 – 6.2 |
| 12 Apr 13 & 15 |
Synthesis 5: Anticipating Results, Loops, Design Guidelines, Functional Mismatches, and Design Partitioning | Text: pp. 314-339 Std-1: B Homework #6 |
| 13 Apr 20 & 22 |
Design 1: Selected Design Examples on Datapath Controllers, Digital Processors, and Arithmetic Processors
Project Review / Help Session (see course website for location of April 22nd class) |
Text: pp. 347-401, 457-756 |
| 14 Apr 27 & 29 |
Design 2: Postsynthesis Design Validation, Timing Verification, Static Timing Analysis, Eliminating Timing Violations, False Paths | Text: pp. 765-785 Synopsys On-line Documentation |
| 15 May 4 & 6 |
Physical Layout Issues: Interconnects, Partitioning, Floorplanning, Placement, Global and Detailed Routing
Final Review |
Synopsys On-line Documentation |
| Monday May 10 2:45pm |
FINAL EXAM | Chapters 1-10, 12 Lecture Notes Web Materials |