Technology mapping for LUT-based FPGAs can be formulated as DAG covering problem, which is known to be NP-hard. So far, no efficient algorithms exist to solve it exactly. This paper proposes a novel method to compute the lower bound for DAG covering problem by transforming a DAG into a tree graph. A heuristic algorithm using the lower bound is also described. The experimental results show that the proposed method is effective for area and power minimization under depth constraint.