Software simulation of modern processors has become extremely difficult due to the ever increasing scale of processors. Further more, modern processors often contain high speed IOs, which can not be fully verified with only software simulation. With the help of FPGA based platform, the verification and evaluation of processors can be done with a relatively high speed. The FPGA based platform also provides a real environment with a lot of real chips working together for the verification of high speed IOs. In this paper, a multi-FPGA based platform targeting verification and evaluation of Godson-2G processor is introduced. Tactics for a semi-custom partitioning and the design flow are discussed. Method to emulate DDR and HyperTransport PHYs is offered after that. Instrumentation based debugging and the performance evaluations are both presented at the end of this paper.