The efficient automatized application partitioning and mapping process for multiprocesor systems is a challenging task in academics as well as in industry until today. The introduction of reconfigurable hardware in this domain helps to meet the application requirements more efficient due to the method of hardware adaptation at design and runtime. This novel degree of freedom in multiprocessor system-on-chip (MPSoC) technology has to be processed by a suitable toolchain, which helps to hide the complexity of the hardware architecture and its realization alternatives from the developer. This paper shows one approach for a semi-automatized toolchain for the development of the hardware architecture and the application partitioning and mapping. A multistep approach is used to partition the software application. This application modules are then partitioned in a Hardware-Software Codesign process in order to achieve a maximum of perfomance on the local processors and therefore in general for the MPSoC.