This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover re-calibrated over time. The results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as fine as 5ps with precisions up to 25ps.