In an FPGA, the input interconnect block (IIB) is a sparse crossbar that connects a cluster of LUTs to an adjacent routing channel. This paper presents an architectural modification to the IIB which exposes the selection bits of its multiplexors to the user in a restricted way. This allows the user to program a limited amount of shifting and multiplexing functionality onto the IIB. This work has been motivated by recent advances in floating-point datapath synthesis techniques on FPGAs, for which the bottleneck, in terms of area, is the massive left shift required for normalization in the presence of effective subtraction. Using the modified IIB in conjunction with LUTs significantly reduces the amount of logic required to realize these shifters, which improves critical path delay and area utilization. The cost of this approach is a IIB that is larger than one without our modifications; however, this cost is offset for circuits for which a large number of IIBs are configured to exploit the enhanced functionality introduced here.