Clock period of pipelined designs are usually determined by the critical paths to avoid timing errors and guarantee reliable operations. The worst case delays of the slowest pipeline stages cause the clock frequency to be less than the average path delays. This may introduce enormous performance loss if the critical paths rarely happen, and the critical path delays are far larger than the average path delays, which is common for many pipelined circuits. In this paper we present a novel timing error recovery technique that guarantees reliable operation of pipelined designs in presence of any arbitrary number of timing errors in different pipeline stages. We allow the clock frequency to be higher than the worst case; hence increasing the performance. We demonstrate the usefulness of our technique by implementing a pipelined arithmetic circuit with the proposed technique on top of a FPGA board. Our experimental results show that we could successfully increase the clock frequency by 30% with the timing error rate of 13%.