Nanotechnology opens up a new way of scaling CMOS circuits by introducing new materials to CMOS circuits. For example, hybrid circuits between CMOS gates and emerging devices such as carbon nano-tube FETs (CNT-FETs), NEMS relay logic, and emerging memory devices are proposed for future nano-scale Field Programmable Gate Arrays (FPGAs). These hybrid circuits are often in the form of a crossbar array architecture that has superior device area density over conventional CMOS circuits. However, there is a dilemma in using emerging devices like CNT-FETs and NEMS relay transistors in crossbar array architecture: CNT-FETs and NEMs relays are not two-terminal devices, which make them less suitable for crossbar array architecture. Hence, the use of crossbar arrays is limited to connections outside of configurable logic blocks (CLBs). On the other hand, two-terminal diode based logic that suits crossbar arrays lack signal gains and are difficult to implement signal level inversion and restoration. These shortcomings make them more dependent on CMOS circuits for most of logic operations and limit their usage to storage and signal routing only. We present nano-magnetic/CMOS hybrid circuit for FPGAs. Magnetic coupled spin-torque devices (MCSTDs) used in our FPGAs solve the signal gain and signal-level restoration problems, which allows the crossbar array layout to be used throughout the entire FPGA architecture. Our hybrid circuit utilizes the magnetic coupling between neighboring two-terminal devices and enables implementation of complex logic operations. Signal gain is achieved by using asymmetric device dimensions between input and output devices. Area and energy consumption calculation of LUT are performed to demonstrate the merits of the presented Nano-magnetic/CMOS hybrid circuit compared to conventional CMOS. Results show 56% savings in area at comparable energy consumptions when compared with 32nm CMOS technology node.