Chip multiprocessors can be expected to scale to several tens of cores and beyond and need more capable and scalable interconnects to provide performance as well as a rich feature set including support for adaptive and flexible communication and fault-tolerance. 2D mesh and torus are attractive choices but their adoption in manycore processor designs is dependent on a verifiable and robust micro-architecture and a validated set of features. FPGA based systems have recently become a cost-effective, rapid prototyping vehicle for chip multiprocessor architectures. In this paper we present, our FPGA based prototype of a 2D on-die interconnect architecture. Our prototype is a highly configurable full-scale design of the target interconnect that supports configurability of several different micro-architectural options, routing algorithms and traffic characteristics to exercise the interconnect. The prototype is supported by a rich development environment and novel software capabilities including a very detailed performance visualization infrastructure. We demonstrate several configurations on a 6x6 2D network emulator setup.