Reconfigurable computing achieves much higher
performance than software, while maintaining a higher level of
flexibility than hardware. Reconfigurable devices, including
field-programmable gate arrays (FPGAs), contain an array of
computational elements whose functionality is determined through
multiple programmable configuration bits. These elements,
sometimes known as logic blocks, are connected using a set of routing
resources that are also programmable. In this way, custom digital
circuits can be mapped to the reconfigurable hardware by computing the
logic functions of the circuit within the logic blocks, and using the
configurable routing to connect the blocks together to form the
necessary circuit. Later in either the same or a different
application, the hardware can be re-programmed to implement an entirely
different circuit.
The projects listed below fall under the heading of reconfigurable
architecture or reconfigurable computing research. Many
applications for this research are envisaged, among them:
- powerful hand-held, automotive, and other embedded media devices,
able to
play music, video, and 3D games at high frame/bit rates with low power
consumption to increase battery life
- powerful stand-alone FPGAs that will further shrink the gap
between ASICs and FPGAs, used to efficiently implement upgradeable
hardware or low-volume designs
- automatic system-on-a-chip (SoC) generation tools, providing fast
and efficient design solutions to decrease time-to-market while
increasing device efficiency
Multi-Logic FPGAs
Transistors are becoming smaller and faster, which is leading some in
the FPGA community to consider logic as "free", and the overhead as
centering in the routing structures. By including a variety of
more complex logic structures, we plan to reduce the amount of routing
required in FPGAs to achieve more area-, performance-, and
power-efficient FPGA designs for embedded or stand-alone use.
Heterogeneous FPGA Tools
Most FPGA tools, such as technology mapping and place and route tools,
focus on LUT-based homogenous FPGAs. However, there is increasing
research in embedded custom resources (such as multipliers and RAM
blocks) as well as non-LUT fabrics. This work will concentrate on
adapting the VPR tool
from the University of Toronto to handle heterogeneous architectures.
OS Support for Reconfigurable Computing
Research in the reconfigurable computing area generally assumes that
only a single thread of a single application will be accessing the
reconfigurable hardware at any given time. However, as
reconfigurable computing becomes mainstream, this assumption will not
remain accurate. The operating system and drivers for the
reconfigurable hardware must negotiate the use of the hardware across
different threads or tasks. Configuration overhead management
techniques must also be adapted for multi-tasking situations.
Finally, dynamic program partitioning will be investigated. This
technique would allow the operating system to choose at runtime if a
section of application code should be run on the reconfigurable
hardware or executed on the host processor, depending on the
availability of each.
Embedded Design Partitioning For Domain-Specific SoC Generation
Previous efforts in partitioning for reconfigurable computing have
focused on dividing applications into sections which usually perform
well on a processor, and sections which usually perform well on
reconfigurable logic. However, if the resources on a
domain-specific system-on-a-chip (SoC) are to be automatically
generated, this opens a new possibility. The resources, both
processor and reconfigurable logic, can be tailored to specific
applications. The best partitioning will depend on the resources
chosen for the design, while the best resources for the design will
depend on the application partitioning. Therefore, the resource
choice and application partitioning are inter-dependent
operations. This research will involve examining the relation of
resource choice and application partitioning for automatic
domain-specific SoC design.