FPGA 2010: Program

Monday Feburary 22, 2010
10:10 AM    Poster Session 1: Applications
   Memory Efficient String Matching: A Modular Approach on FPGAs
Hoang Le,  Edward Yang,  Viktor Prasanna
USC
   A Multi-FPGA Based Platform for Emulating a 100M-transistor-scale Processor with High-speed Peripherals
Huandong Wang,  Xiang Gao,  Yunji Chen,  Dan Tang,  Weiwu Hu
Institute of Computing Technology, Chinese Academy of Sciences
   Towards 5ps Resolution TDC on a Dynamically Reconfigurable FPGA
Marc-André Daigneault and Jean Pierre David
École Polytechnique de Montréal
   An Architecture for Graphics Processing in an FPGA
Marcus Dutton and David Keezer
Georgia Institute of Technology
   FPGA Implementation of Highly Parallelized Decoder Logic for Network Coding
Sunwoo Kim and Won W. Ro
School of Electrical and Electronics Engineering, Yonsei University
   Application of a Reconfigurable Computing Cluster to Next Generation Genome Sequencing
Kristian Stevens1,  Henry Chen2,  Terry Filiba2,  Peter McMahon3,  Yun Song2
1UC Davis, 2UC Berkeley, 3Stanford
   Parallel data sort using networked FPGAs
Janardhan Singaraju and John Chandy
University of Connecticut
   A WiMAX/LTE Compliant FPGA Implementation of a High-Throughput Low-Complexity 4x4 64-QAM Soft MIMO Receiver
Vadim Smolyakov,  Dimpesh Patel,  Mahdi Shabany,  Glenn Gulak
University of Toronto
   FPGA based Chip Emulation System for Test Development of Analog and Mixed Signal Circuits
Rahul Bhattacharya,  Santosh Biswas,  Siddhartha Mukhopadhyay
author
   LambdaRank Acceleration for Relevance Ranking in Web Search Engines
Jing Yan1,  Ning-Yi Xu2,  Xiong-Fei Cai2,  Rui Gao2,  Yu Wang1,  Rong Luo1,  Feng-Hsiung Xu2
1Tsinghua University, 2Microsoft Research Asia
   Implementing Dynamic Information Flow Tracking on Microprocessors with Integrated FPGA Fabric
Skyler Schneider and G. Edward Suh
Cornell University
3:15 PM    Poster Session 2: High-level Abstractions and CAD Tools
   A Reconfigurable Computing Paradigm for Long Lifecycle Electronic Products
Rahul Razdan
University of Florida
   Automatic Tool Flow for Shift-Register-LUT Reconfiguration, Making Run-time Reconfiguration Fast and Easy
Brahim Al Farisi,  Karel Bruneel,  Harald Devos,  Dirk Stroobandt
Ghent University
   Odin II - An Open-source Verilog HDL Synthesis Tool for FPGA CAD Flows
Peter Jamieson1 and Kenneth Kent2
1Miami university, 2University of New Brunswick
   Reconfigurable Custom Floating-Point Instructions
Zhanpeng Jin1,  Richard Neil Pittman2,  Alessandro Forin2
1University of Pittsburgh, 2Microsoft Research
   A Semi-Automatic Toolchain for Reconfigurable Multiprocessor Systems-on-Chip: Architecture Development and Application Partitioning
Diana Goehringer1,  Michael Huebner2,  Michael Benz1,  Juergen Becker2
1Fraunhofer FOM, 2ITIV, Universität Karlsruhe (TH)
   A Dependency Graph based Methodology for Parallelizing HLL Applications on FPGA
Sunita Chandrasekaran,  Shilpa Shanbagh,  Douglas Leslie Maskell
NTU
   LUT-Based FPGA Technology Mapping for Reliability
Jason Cong and Kirill Minkovich
UCLA
   Aggressive Overclocking Support using a Novel Timing Error Recovery Technique on FPGAs
Amir Masoud Gharehbaghi,  Bijan Alizadeh,  Masahiro Fujita
University of Tokyo
   Design space exploration of throughput-optimized arrays from recurrence abstractions
Arpith Jacob,  Jeremy Buhler,  Roger Chamberlain
Washington University in St. Louis
   Multiplier Architectures for FPGA Double Precision Functions
Mohd Yusuf Abdul Hamid and Martin Langhammer
Altera
   A Heuristic Algorithm for LUT-based FPGA Technology Mapping using the Lower Bound for DAG Covering Problem
Taiga Takata1 and Yusuke Matsunaga2
1Kyushu University, 2Kyushu Univerisity
Tuesday Feburary 23, 2010
9:45 AM    Poster Session 3: Architecture and Design Studies
   High-performance FPGA Based on Novel DSS-MOSFET and Non-volatile Configuration Memory
Shinichi Yasuda,  Tetsufumi Tanamoto,  Kazutaka Ikegami,  Atsuhiro Kinoshita,  Keiko Abe,  Hirotaka Nishino,  Shinobu Fujita
Toshiba Corporation
   Design and Evaluation of a Parameterizable NoC Router for FPGAs
Mike Brugge and Mohammed Khalid
University of Windsor
   Energy Reduction with Run-Time Partial Reconfiguration
Shaoshan Liu1,  Richard Neil Pittman2,  Alessandro Forin2
1University of California, Irvine, 2Microsoft Research
   Minimizing Partial Reconfiguration Overhead with Fully Streaming DMA Engines and Intelligent ICAP Controller
Shaoshan Liu1,  Richard Neil Pittman2,  Alessandro Forin2
1University of California, Irvine, 2Microsoft Research
   Heterogeneous-ASIF: An Application Specific Inflexible FPGA using Heterogeneous logic blocks
Husain Parvez,  Zied Marrakchi,  Habib Mehrez
LIP6/UPMC
   Scalable Architecture for Programmable Quantum Gate Array
David McCluskey1,  Mingjie Lin1,  Yaling Ma2
1UC Berkeley, 2Clemson University
   User-programmable Input Interconnect Blocks: Migrating Shifting and Multiplexing Functionality from LUTs into Local Interconnect
Nithin George1,  Hadi Parandeh-Afshar1,  Philip Brisk2,  Paolo Ienne1
1EPFL, 2University of California, Riverside
   Fine-Grained vs. Coarse-Grained Shift-and-Add Arithmetic in FPGAs
Julien Lamoureux,  Scott Miller,  Mihai Sima
University of Victoria
   DRAM-Based FPGA Enabled by Three-Dimensional (3D) Memory Stacking
Yangyang Pan and Tong Zhang
Rensselaer Polytechnic Institute
   Modeling and Simulation of Nano Quantum FPGAs
Mohammed Niamat,  Sowmya Panuganti,  Tejas Raviraj
University of Toledo
   Nano-Magnetic Non-Volatile CMOS Circuits for Nano-Scale FPGAs
Larkhoon Leem,  James A. Weaver,  Metha Jeeradit,  James S. Harris
Stanford University
   FPGA-Based Prototyping of a 2D MESH / TORUS On-Chip Interconnect
Donglai Dai,  Aniruddha Vaidya,  Roy Saharoy,  Seungjoon Park,  Dongkook Park,  Hariharan L Thantry,  Ralf Plate,  Elmar Maas,  Akhilesh Kumar,  Mani Azimi
Intel Corporation